o
    RhX                     @   s   d Z ddlZddlmZmZmZmZmZmZ ddl	m
Z
mZmZmZmZmZmZmZmZ g dZG dd deZG dd	 d	eZG d
d deZdS )z
    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-2025 by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
    N)
RegexLexerbygroupsincludeusingthiswords)	TextCommentOperatorKeywordNameStringNumberPunctuation
Whitespace)VerilogLexerSystemVerilogLexer	VhdlLexerc                   @   s  e Zd ZdZdZddgZdgZdgZdZdZ	dZ
d	ejd
fdefdeejefdejfdejfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefdejfdeeeje fdeeeje d fe!d!d"d#efe!d$d%d"d&ejfe!d'd(d"d&ej"fe!d)d"d#ej#fd*ej$fd+efd,efgd-ed.fd/ejfd0efdeejefd1efgd2ejfd3ejfd4ejd.fd5ejfd6ejfd7ed.fgd8ejd.fgd9Z%d:d; Z&d<S )=r   z?
    For verilog source code with preprocessor directives.
    verilogvz*.vztext/x-verilogz%https://en.wikipedia.org/wiki/Verilogz1.4(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`definemacro\s+(\\)(\n)/(\\\n)?/(\n|(.|\n)*?[^\\]\n)/(\\\n)?[*](.|\n)*?[*](\\\n)?/[{}#@]L?"string4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?[~!%^&*+=|?:<>/-][()\[\],.;\']`[a-zA-Z_]\w*^(\s*)(package)(\s+)^(\s*)(import)(\s+)import)qalwaysalways_comb	always_ffalways_latchandassign	automaticbeginbreakbufbufif0bufif1casecasexcasezcmosconstcontinuedeassigndefaultdefparamdisabledoedgeelseendendcaseendfunctionendgenerate	endmodule
endpackageendprimitive
endspecifyendtableendtaskenumeventfinalforforceforeverforkfunctiongenerategenvarhighz0highz1ifinitialinoutinputintegerjoinlarge
localparammacromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpacked	parameterpmosposedge	primitivepull0pull1pulldownpulluprcmosrefreleaserepeatreturnrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecify	specparamstrengthr   strong0strong1structtabletasktrantranif0tranif1typetypedefunsignedvarvectoredvoidwaitweak0weak1whilexnorxor\bsuffix)
accelerateautoexpand_vectornets
celldefinedefault_nettyper@   elsifendcelldefineendif
endprotectendprotectedexpand_vectornetsifdefifndefr   noacceleratenoexpand_vectornetsnoremove_gatenamesnoremove_netnamesnounconnected_driveprotect	protectedremove_gatenamesremove_netnamesresetall	timescaleunconnected_driveundef`)prefixr   )4bits
bitstorealbitstoshortrealcountdriversdisplayfclosefdisplayfinishfloorfmonitorfopenfstrobefwrite
getpatternhistoryincsaverZ   itorkeylistlogmonitor
monitoroff	monitoronnokeynologprinttimescalerandomreadmembreadmemhrealtime
realtobitsresetreset_countreset_valuerestartrtoisavescalescopeshortrealtobits
showscopesshowvariablesshowvars	sreadmemb	sreadmemhstimestopstrobetime
timeformatwritez\$)byteshortintintlongintr[   r   bitlogicregsupply0supply1tritriandtriortri0tri1trireguwirewirewandworshortrealrealr   [a-zA-Z_]\w*:(?!:)\$?[a-zA-Z_]\w*\\(\S+)"#pop/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})	[^\\"\n]+\\[^/\n]+/[*](.|\n)*?[*]/z//.*?\n/	(?<=\\)\n\n	[\w:]+\*?rootr   r   r'   c                 C   s8   d}d| v r
|d7 }d| v r|d7 }d| v r|d7 }|S )z`Verilog code will use one of reg/wire/assign for sure, and that
        is not common elsewhere.r   r   g?r   r-    )textresultr  r  U/home/air/sanwanet/backup_V2/venv/lib/python3.10/site-packages/pygments/lexers/hdl.pyanalyse_text   s   zVerilogLexer.analyse_textN)'__name__
__module____qualname____doc__namealiases	filenames	mimetypesurlversion_added_wsr	   Preprocr   r   r   EscapeSingle	Multiliner   Charr   FloatHexBinIntegerOctr
   r   Constantr   	Namespacer   r   BuiltinTypeLabeltokensr  r  r  r  r  r      s    

	
N

	br   c                
   @   sD  e Zd ZdZdZddgZddgZdgZdZdZ	d	Z
g d
eeejdfdeeejefdeeejedfdefdeejefdejfdejfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefed d!d"ejfd#efd$e j!fed%d!d"efd&eej"ee j#fd'eej"ee j#fd(eej"eeee j#fed)d!d"ej$fed*d!d"ejfed+d!d"e j%fd,e j&fd-e fd.e fd/ed0fd1ejfd2efdeejefd3efgd4ejfd5ejfd6ejd0fd7ejfd8ejfd9ed0fgd:e jd0fgd;Z'd<S )=r   zi
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.
    systemverilogsvz*.svz*.svhztext/x-systemverilogz+https://en.wikipedia.org/wiki/SystemVerilog1.5r   z^(\s*)(`define)r   r%   r&   r'   r   r   r   r   r   r   r   r   r    r!   z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*r"   )insidedistr   r   z[()\[\],.;\'$]r$   )	accept_onaliasr(   r)   r*   r+   r,   assertr-   assumer.   beforer/   bindbinsbinsofr0   r1   r2   r3   r4   r5   r6   cellcheckerclockingr7   config
constraintcontextr9   cover
covergroup
coverpointcrossr:   r;   r<   designr=   r>   r?   r@   rA   rB   
endcheckerendclocking	endconfigrC   rD   endgroupendinterfacerE   rF   rG   
endprogramendpropertyendsequencerH   rI   rJ   rK   
eventuallyexpectexportexternrM   first_matchrN   rO   foreachrP   rQ   forkjoinrR   rS   rT   globalrU   rV   rW   iffifnoneignore_binsillegal_binsimplies
implementsr'   incdirr   rX   rY   rZ   instanceinterconnect	interface	intersectr\   join_any	join_noner]   letliblistlibrarylocalr^   r_   matchesr`   modportra   rb   rc   nettypenewnexttimerd   re   noshowcancelledrf   rg   rh   nullri   rj   packagerk   rl   rm   rn   ro   priorityprogrampropertyr   rp   rq   rr   rs   pulsestyle_ondetectpulsestyle_oneventpurerandrandcrandcaserandsequencert   ru   	reject_onrv   rw   restrictrx   ry   rz   r{   r|   r}   s_alwayss_eventually
s_nexttimes_untils_until_withr~   sequenceshowcancelledr   softsolver   r   staticstrongr   r   r   supersync_accept_onsync_reject_onr   taggedr   r   
throughouttimeprecisiontimeunitr   r   r   r   unionuniqueunique0until
until_withuntypeduser   virtualr   
wait_orderweakr   r   r   wildcardwithwithinr   r   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!r   r   chandler8   rL   r   r[   r   r   r   r   r   r   	shortrealr   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   wor)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)z$exitz$finishz$stopz	$realtimez$stimez$timez$printtimescalez$timeformatz$bitstorealz$bitstoshortrealz$castz$itorz$realtobitsz$rtoiz$shortrealtobitsz$signedz	$unsignedz$bitsz$isunboundedz	$typenamez$dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz$assertfailonz$assertkillz$assertnonvacuousonz
$assertoffz	$assertonz$assertpassoffz$assertpassonz$assertvacuousoffz$changedz$changed_gclkz$changing_gclkz$falling_gclkz$fellz
$fell_gclkz$future_gclkz$pastz
$past_gclkz$rising_gclkz$rosez
$rose_gclkz$sampledz$stablez$stable_gclkz$steady_gclkz$coverage_controlz$coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez$get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez$dist_erlangz$dist_exponentialz$dist_normalz$dist_poissonz$dist_tz$dist_uniformz$randomz$q_addz$q_examz$q_fullz$q_initializez	$q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz	$displaybz	$displayhz	$displayoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz	$sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz	$readmembz	$readmemhz
$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvarsr   r   r   r   r  r  r  r  r  r  z//.*?$r  r  r	  r
  r  N)(r  r  r  r  r  r  r  r  r  r  r  r   r   r	   r  r   r(  r   r  r  r   r   r!  r   r"  r$  r&  r%  r#  r
   r   Wordr   r'  DeclarationClassr*  r)  r+  r,  r  r  r  r  r      s    	
 ")*NPRU	
ajMN ;  <  =  @

	 
r   c                   @   s  e Zd ZdZdZdgZddgZdgZdZdZ	e
je
jB Zdefd	eejefd
ejfdejfdejfdefdejfdefdefdeeeejfdeeeefdeeeejefdeeeejfdeejejfedddejfdeeeejfdeeeejeeeejee	fdeejeeefdeeeedfe de de d d!efge dd!ejfdefd"ed#fged$ddej!fged%ddefgd&e"j#fd'e"j#fd(e"j$fd)e"j%fd*e"j&fd+e"j'fgd,Z(d-S ).r   z
    For VHDL source code.
    vhdlz*.vhdlz*.vhdztext/x-vhdlz"https://en.wikipedia.org/wiki/VHDLr/  r   r   z--.*?$r   z'(U|X|0|1|Z|W|L|H|-)'r"   z
'[a-z_]\w*r#   z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))stdieeeworkr   r   z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)endblocktypeskeywordsnumbersz	[a-z_]\w*;r  )booleanr   	characterseverity_levelr[   r   delay_lengthnaturalpositiver   
bit_vectorfile_open_kindfile_open_status
std_ulogicstd_ulogic_vector	std_logicstd_logic_vectorr   r   )_absaccessafterr3  allr,   architecturearrayr4  	attributer/   blockbodybufferbusr4   	componentconfigurationconstant
disconnectdowntor@   r   rA   entityexitfilerN   rR   rS   genericgroupguardedrW   impureininertialrY   islabelrd  linkageliteralloopmapmodrb   ri  nextre   rf   rl  ofonopenri   othersoutrm  port	postponed	procedureprocessrs  rangerecordregisterrejectremrx   rolrorselectseveritysignalsharedslasllsrasrlsubtypethento	transportr   unitsr  r  variabler   whenr   r  r   r   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r  r  r  r  r  N))r  r  r  r  r  r  r  r  r  r  re	MULTILINE
IGNORECASEflagsr   r   r   r  r	   r  r   r!  r
   r   	Attributer   r   r(  r   r  r   r   r   r*  r   r%  r"  r#  r&  r$  r,  r  r  r  r  r   u  s    
'	
r   )r  r  pygments.lexerr   r   r   r   r   r   pygments.tokenr   r	   r
   r   r   r   r   r   r   __all__r   r   r   r  r  r  r  <module>   s    
 ,~ d